The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), are scaled down through various technology nodes, strained source/drain features have been implemented using epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Fabricating a MOSFET could include epitaxially growing a silicon layer in a source and drain region of an n-type device, and epitaxially growing a silicon germanium layer (SiGe) in a source and drain region of a p-type device. This can be referred to as a dual-epi process. Conventional techniques form lightly doped source and drain (LDD) regions for the n-type and p-type devices, respectively, prior to the dual-epi process (for example, before forming the Si epi and SiGe epi layers). Although existing approaches for forming LDD regions for IC devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.